Silicon CMOS device technology has shrunken device dimensions by more than an order of magnitude, and is expected to continue to shrink device dimensions down into the sub-5 nm range within the decade. While continuing advances in manufacturing has enabled the reduction in device dimensions, device scaling poses serious challenges at the circuit and system levels. Challenges include reduced power supply voltages, increased leakage currents, decreased reliability, and severely increased power density of integrated systems.
FIG. 1 illustrates data plots of power supply voltage level versus device dimension (shown as trace 105) and power density versus device dimension (shown as trace 110). As device dimensions shrunk from about 0.5 um down to about 0.13 um (shown in span 115), a technique known as constant field scaling was used to scale power supply voltage level along with the shrinking device dimensions. In constant field scaling, the power supply voltage levels scale in proportion with the device dimension. An added bonus with constant field scaling as device dimensions shrunk from 0.5 um to 0.13 um is that power density remained substantially constant.
Then, as device dimensions shrunk from about 130 nm down to about 32 nm (shown as span 120), constant field scaling was no longer effective, since the rapid drop in power supply voltage levels made integrated circuits susceptible to noise and presented reliability issues. Instead, power supply voltage levels were kept nearly constant while drive current per device width increased. Performance boosters, such as strained substrate technology, and so forth, were used to help increase drive current per device width. The nearly constant power supply voltage along with increased drive current per device width has led to a dramatic increase in power density, which may lead to problems such as heat dissipation from the integrated circuit as well as potentially decreased device life due to overheating.
Clearly, the drastic increase in power density may not be able to continue as device dimensions continue to shrink down to 32 nm and below (shown as span 125) due to heat related problems. Ideally, the power density should remain constant or even decrease as device dimensions continue to decrease (shown as trace 130). In order to achieve relatively constant power density, it may be necessary to reduce power supply voltage levels (shown as trace 135).